XAUI

10 Gigabit Attachment Unit Interface (XAUI /ˈzi/ ZOW-ee) is a standard for extending the XGMII (10 Gigabit Media Independent Interface) between the MAC and PHY layer of 10 Gigabit Ethernet (10GbE) defined in Clause 47 of the IEEE 802.3 standard. The name is a concatenation of the Roman numeral X, meaning ten, and the initials of "Attachment Unit Interface".

The purpose of the XGMII Extender, which is composed of an XGXS (XGMII Extender Sublayer) at the MAC end, an XGXS at the PHY end and a XAUI between them, is to extend the operational distance of the XGMII and to reduce the number of interface signals. Applications include extending the physical separation possible between MAC and PHY components in a 10 Gigabit Ethernet system distributed across a circuit board.

Operation[]

XGMII Extender has the following characteristics:

The following is a list of the major concepts of XGXS and XAUI:

RXAUI[]

Reduced Pin eXtended Attachment Unit Interface (RXAUI) is a proprietary modification created by Marvell[2] and Dune Networks[3] (later acquired by Broadcom[4]) aimed to increase the port density by decreasing the interface pin count. The four lanes of the standard XAUI running at 3.125 Gbit/s are replaced by two lanes at 6.25 Gbit/s. Thus 16 pins of an integrated circuit (4 transmit + 4 receive differential pairs) can provide either one XAUI port or two RXAUI ports.

The specification also defines a XAUI to RXAUI adapter, and provides an implementation as Verilog RTL code[2]. FPGA vendors are offering their own implementations as IP blocks.[5][6]

Applications[]

Intended Use[]

The implementation of XAUI as an optional XGMII Extender is primarily intended as a chip-to-chip (integrated circuit to integrated circuit) interface implemented with traces on a printed circuit board. Where the XGMII is electrically limited to distances of approximately 7 cm, the XGMII Extender allows distances up to approximately 50 cm.

Rate of operation[]

The XGMII Extender supports the 10 Gbit/s data rate of the XGMII. The 10 Gbit/s MAC data stream is converted into four lanes at the XGMII (by the Reconciliation Sublayer for transmit or the PHY for receive). The byte stream of each lane is 8b/10b encoded by the XGXS for transmission across the XAUI at a nominal rate of 3.125 gigabaud. The XGXS at the PHY end of the XGMII Extender (PHY XGXS) and the XGXS at the RS end (DTE XGXS) may operate on independent clocks.

Allocation of functions[]

The XGMII Extender is transparent to the Reconciliation Sublayer and PHY device, and operates symmetrically with similar functions on the DTE transmit and receive data paths. The XGMII Extender is logically composed of two XGXSs interconnected with a XAUI data path in each direction. One XGXS acts as the source to the XAUI data path in the DTE transmit path and as the destination in the receive path. The other XGXS is the destination in the transmit path and source in the receive path. Each XAUI data path is composed of four serial lanes. All specifications for the XGMII Extender are written assuming conversion from XGMII to XAUI and back to XGMII, but other techniques may be employed provided that the result is that the XGMII Extender operates as if all specified conversions had been made. One example of this is the use of the optional XAUI with the 10GBASE-LX4 8b/10b PHY, where the XGXS interfacing to the Reconciliation Sublayer provides the PCS and PMA functionality required by the PHY. An XGXS layer is not required at the PHY end of the XAUI in this case. However, means may still be required to remove jitter introduced on the XAUI in order to meet PHY jitter requirements.

See also[]

References[]

  1. ^ "Clause 47. XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachment Unit Interface (XAUI)". IEEE Std 802.3-2008 Section 4 (PDF). Institute of Electrical and Electronics Engineers. 2008. pp. 211–224. Retrieved May 9, 2011.
  2. ^ a b Marvell MV-S 105386-00 RXAUI Interface and RXAUI Adapter Specifications
  3. ^ Dune Networks DN-DS-RXAUI-Spec v1.0, RXAUI - Reduced Pin XAUI
  4. ^ Broadcom buys Dune Networks for $178M to make insanely fast networking chips
  5. ^ Xilinx, LogiCORE IP RXAUI v2.1
  6. ^ Altera, 10 Gigabit Reduced XAUI PCS Core Product Brief

External links[]