This article needs attention from an expert on the subject. The specific problem is: Still an issue regarding 10 nm/7 nm terminology that isn't addressed in the 10-nanometre and 7-nanometre is a deviation from the International Technology Roadmap for Semiconductors definitions. In short, 7 nm Samsung/TSMC is equivalent to 10 nm Intel. Thus treating 10 nm Intel and 7 nm Samsung/TSMC at different articles due to marketing material not real measurements seems to be incorrect, specially when the pages refer to ITRS roadmap (duplicate note at other affected article). (April 2019)
In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the 10 nm process as the MOSFET technology node following the 14 nm node. "10 nm class" denotes chips made using process technologies between 10 and 20 nm.
All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of 10 nm-class chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of 10 nm chips in 2016, and Intel later began production of 10 nm chips in 2018.
Since 2009, however, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch. For example, GlobalFoundries' 7 nm process is similar to Intel's 10 nm process, thus the conventional notion of a process node has become blurred. TSMC and Samsung's 10 nm processes are somewhere between Intel's 14 nm and 10 nm processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.
Egyptian-American engineer Mohamed Atalla and Korean-American engineer Dawon Kahng (the original inventors of the MOSFET in 1959) in 1962 demonstrated a device that has a metallic layer with nanometric thickness sandwiched between two semiconducting layers, with the metal forming the base and the semiconductors forming the emitter and collector. They deposited metal layers (the base) on top of single crystal semiconductor substrates (the collector), with the emitter being a crystalline semiconductor piece with a top or a blunt corner pressed against the metallic layer (the point contact). With the low resistance and short transit times in the thin metallic nanolayer base, the devices were capable of high operation frequency compared to bipolar transistors. The device demonstrated by Atalla and Kahng deposited gold (Au) thin films with a thickness of 10 nm on n-type germanium (n-Ge) and the point contact was n-type silicon (n-Si).
In 2002, an international team of researchers at UC Berkeley, including Shibly Ahmed (Bangladeshi), Scott Bell, Cyrus Tabery (Iranian), Jeffrey Bokor, David Kyser, Chenming Hu (Taiwan Semiconductor Manufacturing Company), and Tsu-Jae King Liu, demonstrated the first FinFET with 10 nm gate length.
The ITRS's original naming of this technology node was "11 nm". According to the 2007 ion of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM should be 11 nm.
In actuality, "10 nm" as it is generally understood in 2018 is only in high-volume production at Samsung. GlobalFoundries has skipped 10 nm, Intel has not yet started high-volume 10 nm production, due to yield issues, and TSMC has considered 10 nm to be a short-lived node, mainly dedicated to processors for Apple during 2017–2018, moving on to 7 nm in 2018.
There is also a distinction to be made between 10 nm as marketed by foundries and 10 nm as marketed by DRAM companies.
In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a 10 nm-class process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm". On 17 October 2016, Samsung Electronics announced mass production of SoC chips at 10 nm. The technology's main announced challenge has been triple patterning for its metal layer.
On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone which uses the company's version of the 10 nm processor. On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the 10 nm FinFET process.
On September 12, 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a 10 nm FinFET process and containing 4.3 billion transistors on a die of 87.66 mm2.
In April 2018, Intel announced a delay in volume production of 10 nm mainstream CPUs until sometime in 2019. In July the exact time was further pinned down to the holiday season. In the meantime, however, they did release a low-power 10 nm mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.
In June 2018 at VLSI 2018, Samsung announced their 11LPP and 8LPP processes. 11LPP is a hybrid based on Samsung 14 nm and 10 nm technology. 11LPP is based on their 10 nm BEOL, not their 20 nm BEOL like their 14LPP. 8LPP is based on their 10LPP process.
|ITRS Logic Device
Ground Rules (2015)
|Process name||16/14 nm||11/10 nm||10 nm||11 nm||8 nm||10 nm||10 nm[a]|
|Transistor density (MTr / mm²)||Unknown||Unknown||51.82||54.38||61.18||52.51||100.8[b]|
|Transistor Gate Pitch (nm)||70||48||68||?||64||66||54|
|Interconnect pitch (nm)||56||36||51||?||?||44||36|
|Transistor Fin Pitch (nm)||42||36||42||?||42||36||34|
|Transistor Fin Height (nm)||42||42||49||?||?||Unknown||53|
Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their 10 nm process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their 10 nm process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed these values to be false and they have been updated accordingly. In addition, the transistor fin height of Samsung's 10 nm process was updated by MSSCORPS CO at SEMICON Taiwan 2017.
For the DRAM industry, the "10 nm" node is often referred to as "10 nm-class" and this dimension generally refers to the half-pitch of the active area. The "10 nm" foundry structures are generally much larger. Samsung is also the most prominent player for 10 nm-class DRAM.[failed verification]
Samsung 10LPE process
|MOSFET manufacturing processes||Succeeded by|